本書是作者多年來在得克薩斯大學奧斯汀分校講授數字繫統設計課程的經驗積累。書中總結了VHDL語言的常規和**文法特點，介紹了數字繫統中運算部件從簡單到復雜的設計方法，基於SM圖實現復雜控制邏輯的VHDL設計方法，以及運算部件和控制邏輯的繫統整合方法。書中提供了大量的設計實例可供參考，適用於本科高年級同學和研究生對數字繫統進行VHDL設計與實現。

本書對原著進行了結構調整，使之更適合作為本科雙語教學教材。第1 章首先回顧了邏輯設計基本原理，第2章和第3章分別講解了VHDL基本知識 和高級主題，第4章為簡單設計實例，第5章討論狀態機，第6章討論浮點數 運算，第7章討論硬件測試和可測試性設計，第8章給出了一些高級設計實 例。全書將工業標準硬件描述語言VHDL和數字繫統設計融為一體，較好地 實現了控制邏輯和運算部件的整合設計，並給出了多個設計實例，便於學 生在實踐中得到提高。 本書適合作為高等院校電子、電氣和計算機專業本科生數字繫統設計 類課程的雙語教學教材，也適合作為相關工程技術人員的參考書。

Chapter 1 Review of Logic Design Fundamentals
1.1 Combinational Logic
1.2 Boolean Algebra and Algebraic Simplification
1.3 Karnaugh Maps
1.4 Designing with NAND and NOR Gates
1.5 Hazards in Combinational Circuits
1.6 Flip-Flops and Latches
1.7 Mealy Sequential Circuit Design
1.8 Moore Sequential Circuit Design
1.9 Equivalent States and Reduction of State Tables
1.10 Sequential Circuit Timing
1.11 Tristate Logic and Busses
1.12 Problems
Chapter 2 Introduction to VHDL
2.1 Computer-Aided Design
2.2 Hardware Description Languages
2.3 VHDL Description of Combinational Circuits
2.4 VHDL Modules
2.5 Sequential Statements andVHDL Processes
2.6 Modeling Flip-Flops Using VHDL Processes
2.7 Processes Using Wait Statements
2.8 Two Types of VHDL Delays: Transport and Inertial Delays
2.9 Compilation, Simulation, and Synthesis of VHDL Code
2.10 VHDL Data Types and Operators
2.11 Simple Synthesis Examples
2.12 VHDL Models for Multiplexers
2.13 VHDL Libraries
2.14 Modeling Registers and Counters Using VHDL Processes
2.15 Behavioral and Structural VHDL
2.16 Variables, Signals, and Constants
2.17 Arrays
2.18 Loops in VHDL
2.19 Assert and Report Statements
2.20 Problems
Chapter 3 Additional Topics in VHDL
3.1 VHDL Functions
3.2 VHDL Procedures
3.3 Attributes
3.4 Creating Overloaded Operators
3.5 Multi-Valued Logic and Signal Resolution
3.6 The IEEE 9-Valued Logic System
3.7 SRAM Model Using IEEE 1164
3.8 Model for SRAM Read/Write System
3.9 Generics
3.10 Named Association
3.11 Generate Statements
3.12 Files and TEXTIO
3.13 Problems
Chapter 4 Design Examples
4.1 BCD to Seven-Segment Display Decoder
4.2 A BCD Adder
4.3 32-Bit Adders
4.4 Traffic Light Controller
4.5 State Graphs for Control Circuits
4.6 Scoreboard and Controller
4.7 Synchronization and Debouncing
4.8 A Add-and-Shift Multiplier
4.9 Array Multiplier
4.10 A Signed Integer/Fraction Muliplier
4.11 Keypad Scanner
4.12 Binary Dividers
4.13 Problems
Chapter 5 SM Charts and Microprogramming
5.1 State Machine Charts
5.2 Derivation of SM Charts
5.3 Realization of SM Charts
5.4 Implementation of the Dice Game
5.5 Problems
Chapter 6 Floating-Point Arithmetic
6.1 Representation of Floating-Point Numbers
6.2 Floating-Point Multiplication
6.3 Floating-Point Addition
6.4 Other Floating-Point Operations
6.5 Problems
Chapter 7 Hardware Testing and Design for Testability
7.1 Testing Combinational Logic
7.2 Testing Sequential Logic
7.3 Scan Testing
7.4 Boundary Scan
7.5 Built-In Self-Test
7.6 Problems
Chapter 8 Additional Design Examples
8.1 Design of a Wristwatch
8.2 Memory Timing Models
8.3 A Universal Asynchronous Receiver Transmitter
8.4 Problems
Appendix A
VHDL Language Summary
Appendix B
IEEE Standard Libraries
Appendix C
TEXTIO Package
Appendix D
Projects
References